Reliability Analysis of Logic Network with Multiple Outputs

Reliability has been considered as an important design measure in many technical systems [1 6]. A logic network is one of them [1, 4 6]. One of principal problems in reliability analysis of a logic network is investigation of influence of breakdown of each gate upon the network failure [1, 5 and 6]. The system reliability modeling and calculation of reliability indices and measures are principal steps in such analysis. A real system contains a lot of components. From reliability point of view, the system and all its components can be in one of two possible states: functional (presented as 1) and failed (presented as 0). The dependency between system state and states of its components is defined by the structure function [7 and 8]:


Introduction
Reliability has been considered as an important design measure in many technical systems [1 -6]. A logic network is one of them [1, 4 -6]. One of principal problems in reliability analysis of a logic network is investigation of influence of breakdown of each gate upon the network failure [1, 5 and 6]. The system reliability modeling and calculation of reliability indices and measures are principal steps in such analysis.
A real system contains a lot of components. From reliability point of view, the system and all its components can be in one of two possible states: functional (presented as 1) and failed (presented as 0). The dependency between system state and states of its components is defined by the structure function [7 and 8]: , ,..., : , , where n is the number of system components, x i is the state of component i, for i = 1,2,…,n, and x = (x 1 , x 2 ,…, x n ) is a vector of components states (state vector). The structure function of many systems is monotonic. This means that there exists no situation in which the failure of some components causes the system repair. This type of systems is known as coherent. Coherency is a typical property of many systems in reliability analysis. However, there exist some systems that are noncoherent [9] - [12]. Their structure function is nonmonotonic, which means that there exist situations in which the failure of some component results in system repair. The logic networks are typical example of such systems and, therefore, classical approaches of reliability engineering cannot be used in their analysis [12].
The structure function does not take the availabilities of individual system components into account and, therefore, it allows analyzing only topological characteristics of the system. When other aspects of system availability have to be studied, then the probabilities of working/non-working state of every component should be known: Probabilities p i and q i are known as the availability and unavailability of component i.
When the system structure function and availabilities of all system components are known, then system availability and unavailability can be computed as follows [7 and 8]: The availability is one of the most important characteristics of any system because it defines the proportion of time in which the steady-state system will be working. It can also be used to compute other reliability characteristics, e.g. mean time to failure, mean time to repair, some types of importance measures, etc. [7].
Using relation between the system structure function and its availability (3), the structure function of a logic network with m outputs can be defined in the following way: where ↔ is the symbol of logical biconditional and it can be interpreted in terms of vector logic functions as follows: where F t (y) is the t-th element of the vector logic function F(y), i.e. F t (y) represents the expected value of the t-th output signal, and F t,o (y; x) is the t-th element of the vector logic function F o (y; x) that defines the real value of the t-th output signal (t = 1,2,…,m).

B. Substructure Functions of Logic Network with Multiple Outputs
The structure function (8) and (9) allows analyzing the correlation between values of input signals and the correct work of the network (i.e. correct work of all outputs) on one side and correlation between activity of logic gates and the correct work of all outputs on the other side. However, it can also be useful to analyze these correlations with respect to only one output. Therefore, using notation (9), we can define m substructure functions: that describe the relation between the correct work of the t-th output and values of input signals and operability of individual logic gates. Clearly, according to the previous paragraphs, the structure function of a general logic network can also be defined in the following way: z(x; y) = z 1 (x; y)/ z 2 (x; y)/…/ z m (x; y). (11) According to the previous formula, the structure function of a logic network with multiple outputs can be simply derived from substructure functions of individual outputs.

C. Unreliable Logic Gates
Every logic gate realizes some logic function (e.g. AND, OR, etc.). However, this is true if the gate is functional. Now, assume that the failed gate in mathematical interpretation generates signals that can also be interpreted as values 0 or 1. This assumption implies that the broken gate realizes a logic function too, but it is different from the original one. Therefore, the failure

Logic Network with Multiple Outputs
In reliability analysis of logic networks, the studied system is a logic network of k logic inputs and n logic gates, which realizes a logic function: where k is a number of input signals, y l is the l-th variable of the logic function and it corresponds to the l-th input of the logic network, for l = 1, 2,…,k, and y = (y 1 , y 2 ,…, y k ) is a vector of input signals (input vector). A lot of logic networks have more than one output and realize a set of logic functions. Therefore, the general logic network is a realization of m-dimensional vector logic function: where k is a number of input signals and m is a number of output signals.
With relation to reliability analysis, a logic network has two different types of components: • n logic gates -they can be working or failed; • k inputs -they can be correct or incorrect.
In paper [12], there has been considered assumption that the input signals are always correct and, therefore, only logic gates are relevant system components. Using this assumption, the structure function of a logic network and the Structural Importance Measure (SIMs) of individual logic gates have been defined. However, they have been proposed for networks with only one output. Now, we concentrate on a logic network with m outputs.

A. Structure Function
The output of a real logic network is determined not only by values of inputs but also by proper work of individual logic gates. Therefore, the real output of a logic network has to be defined by logic function F o (y; x) which takes into account not only the values of the input signals (input vector y) but also the states of logic gates of the network (state vector x) [5]: where k is a number of input signals, m is a number of output signals, and n is a count of logic gates that are used in the logic network.
When the expected output F(y) and real output F o (y; x) of a logic network are known, then its availability can be defined as probability that these two output signals have the same values [5]: Similarly, DPLD (14) can be defined for system substructure function as follows: ,. (16) Derivatives (13) -(16) are very similar, but there is a principal difference in their meaning and use. DPLDs (13) and (15) analyze the impact of the failure/repair of given component and, therefore, they can be used in importance analysis to find components with the most influence on the system proper work. On the other hand, DPLDs (14) and (16) are useful in the creation of test cases for detection of failed logic gates, because, when some gates are failed, then these DPLDs reveal situations in which the change of given input signal causes the change of the value of the structure function [12 and 14].

E. Structural Importance Measure
System availability (3) is very important measure that defines the probability that the system is working. However, it does not allow us to find the influence of individual system components on the system activity, i.e. to identify which components are the most important for proper work of the system. For this purpose, there exist other measures that are known as Importance Measures (IMs) [15].
One of the basic IMs is Structural Importance Measure (SIM) that estimates the topological influence of given component on the system work. For noncoherent systems, it is defined as the relative number of situations in which the change of system component state (component failure/repair) results in the system failure [11].
In paper [12], two types of the SIM for logic network with one output have been considered. The first one estimates the topological importance of given component when the exact values of input signals are known. This SIM is defined for given logic gate and given vector s of input signals as follows: where z y = s (x) = z(x; y = s) = z(x;s 1 , s 2 ,…, s k ) and ρ(.) is the function that returns the number of state vectors for which the argument has nonzero, i.e. true value. For example ρ(x 1 0x 2 ) = 3, because the logic function x 1 0x 2 is true for 3 state vectors, i.e. (0,1), (1,0) and (1,1); ρ(x 1 x 2 ) = 1, because the logic function x 1 x 2 has true value only for state vector (1,1). The SIM (17) permits to identify which gates are the most important for given values of input signals, but, it does not allow analyzing the overall influence of given gate on the proper work of the network. For this purpose, another type of the SIM has been defined in paper [12]. Using the SIM (17), this IM is defined in the following way: of a logic gate can be modeled as a change of function realized by the gate [6 and 12].
Consider a logic network of n logic gates. The i-th gate of the network realizes two different functions depending on the state (functional/failed) of the gate: (i) when the gate is functional, then it implements function f i (y), (ii) when it is broken, then it realizes function f i,u (y). Therefore, the unreliable logic gate is a realization of function f i,o (y; x i ) [12]: ; When functions f i,u (y) are known for all logic gates of the network, function F t,o (y; x), which defines the real value of the t-th output of the network, can be obtained simply by replacement of every logic gate in the scheme of the network by functions f i,o (y) of individual gates and then the substructure functions (10) and the structure function (11) can be identified.

D. Direct Partial Logic Derivatives
Direct Partial Logic Derivatives (DPLDs) are part of logical differential calculus that has been developed to analyze dynamic properties of Boolean functions [13]. The structure function can also be interpreted as a Boolean function and, therefore, DPLDs can be used in reliability analysis [8].
In paper [12], two types of DPLDs of the structure function have been considered in the analysis of a logic network. The first one is defined as follows: , ; , ; x y x y x a a j j a j a j where z(a i , x; y) = z(x 1 , x 2 ,…, x i-1 , a, x i+1 ,…, x n ; y), a, j ! {0, 1}. DPLD (13) identifies situations when the failure/repair of given component results system failure/repair [8, 11 and 12]. However, the structure function of a logic network depends not only on states of individual components (logic gates) but also on the values of individual input signals. Therefore, we can define another logic derivative that analyzes situations in which the change of given input results the failure/repair of the logic network: where z(x; a l , y) = z(y; y 1 , y 2 ,…, y l-1 , a, y l+1 ,…, y n ), a, j ! {0, 1}. These two DPLDs can also be defined for individual substructure functions of the system. In this case, DPLD (13) has the following form: , ; , ; ,, (15) and it can be used to detect situations in which the failure/repair of given logic gate results in the failure of the t-th output, i.e. situations when the real value of the t-th output is different from the expected one.
Equations (19) define the expected values of the output signals. Now, we need to find their real values. This can be done simply by replacement of every logical operator using (12). So, we get the next formula for the first output: where f 1,u (y) represents the logic function that is realized by the 1-st logic gate when it is failed and f 2,u (y) represents the logic function realized by the failed 2-nd gate. Similarly, we can identify the real value of the second output.
There are different types of failures in logic networks [5 and 16]. For the simplicity, assume that the failure of the XOR gates results that they will generate only value 1 regardless of the values of input signals while the failure of the AND and OR gates causes that they will generate only 0-signal on the output. Using this assumption, the real outputs of the adder are: In the next step, the substructure functions z 1 (x; y) and z 2 (x; y) can be identified by comparing functions F 1,o (y; x) and The previous equations define the relations between states of individual logic gates, values of input signals and correctness of individual outputs and, therefore, they are useful for analysis of this kind of dependencies. However, they do not allow us to evaluate the reliability of the network as a whole. For this purpose, the structure function has to be found. This can be done using definition (11) where {0, 1} k is the space of all possible input signals.
In the case of a logic network with multiple outputs, definitions (17) and (18) can be used in two ways. Firstly, they can be used with the structure function (8) of the network. In this case, they have the same meaning as those proposed in paper [12] because they analyze the influence of given gate on the whole logic network. On the other hand, the structure function z y = s (x) in (17) can be replaced by the substructure function f t,y = s (x) = =z t (x; y = s) = z t (x;s 1 , s 2 ,…, s k ). In this case, SIM (17) will identify the influence of gate i on the correct value of the t-th output when individual input signals have values s 1 , s 2 ,…, s k and SIM (18) will estimate the total topological influence of component i on the correct value of the t-th output.

F. Structure and Substructure Functions
Consider a one-bit full adder that is implemented according to the scheme depicted in Fig. 1. It has three input signals where y 1 and y 2 represent bit operands and y 3 represents a bit carried from the previous less significant stage, and 2 outputs whose behavior is defined by functions F 1 (y) (an output bit) and F 2 (y) (a carry out bit).
When the DPLDs and numbers of their nonzero elements are computed, then we can calculate the SIMs (17) for individual logic gates (Table 3).
Finally, using the probabilities in Table 1 and the SIMs in Table 3, the overall SIMs (18) of individual logic gates can be computed. These values are computed in Table 4. Table 3 Vectors of Input Signals The Overall SIMs of Logic Gates in the One-bit Adder Table 4 Logic Gate

G. Topological Analysis of the One-bit Full Adder
Consider the one-bit full adder in Fig. 1. Using equations (17) and (18), the topological importance of every gate can be computed if the probabilities of values of input signals are known. For this purpose assume that the input signals have probabilities defined in Table 1.
When we want to analyze the topological importance of individual logic gates, the values of SIMs (17) have to be computed for every combination of input signals for every component. This implies that DPLDs (13) should be computed and, then, numbers of state vectors, for which the DPLDs are true, have to be identified. For illustration, these numbers are presented in Table 2 for the first 3 components.
The Probabilities of Individual Values of Input Signals of the One bit-Adder Table 1 Input signal Probability of value 0 Probability of value 1 y 1 0.5 0.5 y 2 0.5 0.5 Numbers of Nonzero Elements of Individual DPLDs Table 2 Vectors of Input Signals function of the whole network that characterizes the network as a whole because it defines the dependency between proper work of logic gates and the correct values of all outputs. This structure function can be used to estimate network availability or to analyze the importance of individual logic gates for the proper work of the network. The second ones are the substructure functions of individual network outputs. They define the correlation between the proper work of individual logic gates and the correct value of one output signal. These functions can be used to evaluate the influence of logic gates on the value of studied output signal and, therefore, they can be used in importance analysis or in creating scenarios for identification of failed logic gates.
In the last part of this paper, we focused on the use of the structure and substructure functions in importance analysis. We proposed the definitions of the SIM for logic networks with multiple outputs. Our definitions are based on logical differential calculus and they allow identify which components have the most influence on the proper work of the whole network or on the correct value of one concrete output signal from topological point of view. Although results of this paper have more theoretical significance, a case study considered at the end of this paper indicates that our approach is useful and its further development and practical implementation could be beneficial for reliability analysis of logic networks.

Acknowledgment
This work was partially supported by the research grants of Slovak Research and Development Agency SK-PL-0023-12 and VEGA 1/0498/14.
influence. Therefore, we should focus on the XOR gates in other phases of reliability analysis.

Conclusion
Logic networks are special type of systems from reliability point of view because their structure function depends not only on states of their components (logic gates) but also on other characteristics that can be identified as the environment influence. This influence is included in input signals whose values do not depend on the network properties but on the environment in which the network is situated.
Most techniques of reliability engineering assume that the studied system is coherent. However, this assumption is not valid for logic networks because there can exist situations when the failure of some logic gate results that the network begin generate the correct output signal, while, before the failure, the output signal has been incorrect [12]. Therefore, the reliability analysis of logic networks is more complicated than analysis of other types of systems.
One of the principal steps of reliability analysis is identification of the system structure function. In paper [12], there has been proposed a method for this task when the analyzed system is a logic network with one output. That method is based on the assumption that a real logic gate is unreliable and, therefore, its output depends on whether it is working or failed. In this paper, we generalized this concept on logic networks with multiple outputs.
Two types of structure functions can be identified in a logic network with multiple outputs. The first one is the structure